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M
Features
* Allows safe board removal and insertion from a live backplane * Accurate (<1.5%) internal voltage reference for fault detection and precision timing * Programmable foldback current limiting * Programmable circuit breaker current limiting * Auto restart option for all faults * Adjustable Undervoltage lockout thresholds * Adjustable Overvoltage protection threshold * Adjustable Power Good delay * Configurable Power Good output polarity * Low-side drive of an external N-channel FET
MCP18480
-48V Hot Swap Controller
Description
The MCP18480 is a Hot Swap controller that allows boards to be safely removed or inserted from an active backplane using -48V. When PCBs are inserted into a live backplane, highpeak or transient currents from the source are generated due to the charging of the bypass capacitors on the supply. The high transient currents can destroy connectors and capacitors. The high inrush current can pull the input voltage BUS down and reset the system. The MCP18480 solves this problem by controlling the slew rate of the backplane voltage to the board so that these transients are eliminated. This allows boards to be removed and inserted without causing damage to connector pins and input bulk capacitors, in addition to preventing false resets to the other boards on the backplane. The MCP18480 can be used in applications in several areas including: * * * * * * * * Telecom Line Cards Network Switches Network Routers and Servers Base Station Line Cards Power-Over-LAN Power-Over-MDI IP Phone Switches/Routers Mid-Span, Power-Over-MDI
CMOS Technology
* High-Voltage Operation * Temperature range: Industrial (I): -40C to +85C
Packaging
* 20-lead SSOP
Package Type
SSOP
VPOS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENSE RDISCH
OVTH
UVTH UV HYS UVD VREFOUT VREFIN CL ISET TIMER
Two forms of current limit are provided in the MCP18480. These are: * Foldback * Circuit breaker The foldback current-limiting circuit uses an external sense resistor and a voltage that is proportional to the external MOSFET's drain voltage. These are used to keep the MOSFET in its Safe Operating Area (SOA). If the device remains in current limit for a programmed time period, the external N-channel FET is turned off. The option exists to configure the device to automatically restart after a programmed time delay. A programmable catastrophic current limit threshold shuts down the switch (circuit breaker) if excessive current is sensed due to a short-circuit condition.
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MCP18480
VNEG
DS20091B-page 1
MCP18480
Internal comparators are incorporated to add hysteresis for adjusting the Undervoltage Lockout (UVLO) threshold. The external N-channel MOSFET is turned on when the input is below the user-programmable, Overvoltage threshold and above the userprogrammable, Undervoltage threshold. The PWRGOOD pin indicates the status of the MCP18480 and is active when the device has completed power-up and the system is not in an Undervoltage, Overvoltage or current-limit condition. PWRGOOD can be externally configured to either active-high or active-low to accommodate external circuitry (power supplies) that have either enabling logic. A block diagram of the MCP18480 is shown below.
MCP18480 Block Diagram
VPOS
DRAINTH
VPOS
FET Good (Section 6.8.3) BIAS (Section 6.8.8) 12V Regulator 12VOUT 5V Reg. VREFOUT VREFIN ISET Internal Bias Generation 5V OUT Overvoltage Active SENSE GATE Drive (Section 6.8.7) GATE PWRGOOD Output Block (Section 6.8.9) PWRGOOD (1)
VNEG
Undervoltage Active
OVTH
OVO Overvoltage (Section 6.8.2)
5VOUT Current Limit Feedback
ENABLE LATCHOFF
UVTH UVHYS UVD Undervoltage (Section 6.8.1)
RESTART Latch (Section 6.8.6) TIMEOUT
VNEG
VFB SENSE CL Current Limit (Section 6.8.4) Current Limit Timer Circuit Breaker
TIMER RDISCH
Timer (Section 6.8.5)
MCP18480
Note 1:
The PWRGOOD output pin can be either active-high or active-low. This polarity is determined by the voltage (either the level on the VREFIN pin or level on the VNEG pin) on the ISET pin:
- Connecting the external RISET resistor to VREFIN configures the PWRGOOD pin as active-low - Connecting the external RISET resistor to VNEG configures the PWRGOOD pin as active-high
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MCP18480
1.0 ELECTRICAL CHARACTERISTICS
Max. Output Current sourced by VREFOUT pin .....5 mA Max. Output Current sourced by any other Output pin...........................................................25 mA Junction to Ambient, JA (20 pin SSOP Package) Derating ............... 108.1C/W Junction to Case, JC (20 pin SSOP Package) Derating ................. 32.2C/W Lead Temperature, Soldering, 10 seconds ........ 300C
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Ambient Temperature under bias ........ -40C to +85C Storage Temperature ........................ -65C to +150C Voltage on VPOS with respect to VNEG -0.3V to +15.0V Voltage on DVTH, UVTH, VFB, OVO and UVHYS pins with respect to VNEG ..... VNEG - 0.3V to (VPOS + 0.3V) Voltage on VREFIN, CL, SENSE, DRAINTH, ENABLE and RESTART pins with respect to VNEG ........................................................ VNEG - 0.3V to 6V. Total Power Dissipation (Note 1) .................... 800 mW Max. Current out of VNEG pin............................. 80 mA Max. Current into VPOS pin ................................ 50 mA Max. Output Current sunk by Gate pin............... 80 mA Max. Output Current sunk by V REFOUT pin .......... 5 mA Max. Output Current sunk by any other Output pin......................................................... 25 mA Max. Output Current sourced by Gate pin ........ 200 A
Note 1: Power Dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(V DD-V OH) x IOH} + (VOL x IOL)
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, operating temperature: -40C TA +85C (Industrial), Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 F. Param. No. MD001 Parameter Current into shunt regulator that produces VPOS output voltage that meets MD001A specification Regulated Output Voltage Differential of VPOS to VNEG VREFOUT pin output voltage VGATE pin output voltage Voltage on ISET pin Voltage on SENSE pin to trigger current-limiting Sym IPOS1 Min 5 5 Typ (1) -- -- Max 25 25 Units mA Conditions ENABLE pin = 5V ENABLE pin = V NEG V V V V mV mV mV V V V mV VREFIN = 2.5V VREFIN = 2.5V V FB = VNEG V FB = VNEG + 0.25V V FB = VNEG + 0.5V See MD001 Load = 50 A
MD001A MD002 MD010 MD011 MD012A MD012B MD012C MD013 MD014A MD014B MD015
VPOS VREFOUT VGATE VISET VSENSE
10.4 2.463 VPOS - 2 (VREFIN/2) 0.02 40 25 7
12.0 2.5 VPOS -1 VREFIN /2 50 31.0 12 VREFIN VREFIN VREFIN - 0.02 100
13.4 2.538 VPOS (VREFIN /2) +0.02 60 40 17 VREFIN + 0.03 VREFIN + 0.05 VREFIN - 0.005 130
Undervoltage Threshold Overvoltage Threshold rising falling DRAIN Pin Input Threshold Voltage
UVTH OVTH OVTH V DTH
VREFIN - 0.03 VREFIN - 0.05 VREFIN - 0.035 90
Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: Negative current is defined as current sourced by the pin. 3: All voltages are with respect to the V NEG pin voltage.
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MCP18480
DC Characteristics (Continued)
Electrical Specification: Unless otherwise specified, operating temperature: -40C TA +85C (Industrial), Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 F Param. No. MD020 MD021 MD022 MD022A MD022B MD022C MD023 MD024A MD024B UVD pin current TIMER pin current Pull-up Pull-down Pull-down IGATE IUVD ITIMER Parameter DRAIN pin current SENSE pin current GATE pin current Pull-up Sym IDRAIN ISENSE IGATE -30 -9 31 -7 -100 52 -50 -17 49 -10 -160 78 -75 -33 72 -15 -200 104 A A mA A A nA Min -- -- Typ (1) -- -- Max 0.1 0.1 Units A A SENSE pin = VNEG GATE pin = VNEG +4V VFB = VNEG VFB = VNEG + 500 mV Any fault condition UV TH < VREFIN RISET = 125 k, VREFIN = 2.5V RISET = 125 k, VREFIN = 2.5V RDISCH = 1.6 M See MD011 Conditions DRAINTH pin = VNEG
MD025
ISET pin current
IISET
VISET(MIN) RISET(MAX)
--
VISET(MAX) RISET(MIN)
A
Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: Negative current is defined as current sourced by the pin. 3: All voltages are with respect to the V NEG pin voltage.
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MCP18480
DC Characteristics (Continued)
Electrical Specifications: Unless otherwise specified, operating temperature: -40C TA +85C (Industrial), Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 F. Param # MD030 MD031 MD032 MD040 MD041 MD042 MD050 Parameter Input Low Voltage ENABLE pin RESTART pin Input High Voltage ENABLE pin RESTART pin Internal Resistance on UV HYS pin RUVHYS V IH 2.0 2.0 500 50 Input Leakage Current (Notes 2, 3) MD060A MD060B MD070 OVTH, UVTH , VFB, OVO and UVHYS pins VREFIN, CL, SENSE, DRAIN TH, ENABLE and RESTART pins Minimum current into ENABLE pin to disable MCP18480 Output Low Voltage MD080 MD090 MD100 PWRGOOD pin Output High Voltage PWRGOOD pin Offset Voltage at the internal comparator input that is connected to the CL pin. VCL VOH 0.8 VPOS -15 IEN VOL 0 -- -- 0.96 VPOS -- VPOS +15 V mV IOH = 2 mA, 7 mA IPOS 12 mA VFB = 0 0.4 V IOL = 5 mA IIL -1 -- -- -- -- 10 +1 1 30 A A A VNEG VPIN 11V, Pin at high-impedance VNEG VPIN 5V, Pin at hi-impedance IPOS = 5 mA, ENABLE = 0.8V -- -- 1200 100 5.0 5.0 2100 -- V V M VUVTH < VREFIN, IUVHYS = 30 A VUVTH > VREFIN, IUVHYS = 30 A Sym VIL VNEG VNEG -- -- 0.8 0.8 V Min Typ Max Units Conditions
Note 1: All voltages are with respect to the V NEG pin voltage. 2: The leakage currents on the ENABLE and RESTART pins are strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
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DS20091B-page 5
MCP18480
1.1
1.1.1
Timing Parameter Symbology and Load Conditions
TIMING CONDITIONS
The timing parameter symbols have been created using one of the following formats:
The temperature and voltages specified in Table 1-2 apply to all timing specifications, unless otherwise noted. Figure 1-1 specifies the load conditions for the timing specifications.
TABLE 1-1:
1. TppS2ppS T F E
SYMBOLOGY
2. TppS T Time
Frequency Error
Lowercase letters (pp) indicate the device pin. Uppercase letters and their meanings: S F FR H I L Fall Fast Ramp High Invalid (Hi-impedance) Low P R V Z Period Rise Valid Hi-impedance
TABLE 1-2:
AC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 1.0.
AC CHARACTERISTICS
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MCP18480
GND RBYPL 51 k SRS 5V 1 2 RUV2 RUVHYS 3 4 5 6 7 8 9 RISET 124 k Ctimer 680 nF VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET RESTART 20 ENABLE 19 PWRGOOD 18 OVO 17 DRAINTH 16 VFB 15 GATE 14 SENSE 13 RDISCH 12 VNEG 11 RDISCH 1.6 M SEN RPG1 110 k RPG3 680 RPG4 36 k QPG1 MPSA43 QPG2 2N5400 RPG5 36 k RPG6 1500 QPG3 NTE261 GOODPWR CBYPL 100 F 100 V
VIN+ VOUT+
RZ RPOS 4 k CBYP1 + 2 F 78V Transorb ROV1 1.74 M CBYP2 10 nF ROV2 59 k 280 k 30.9 k CUVD 800 nF RUV1 453 k 24.9 k
DC/DC
Converter Module ON/OFF VIN- VOUT-
10 TIMER
MCP18480
RPG2 7.5 k RSENSE 0.01 CG1 RG1 100 nF 10 M1 NTE2388
RGD 18 k CGD 3.3 nF
VNEG
Fuse 10A
RFB2 124 k RDRAIN2 115 k ROVO2 59 k
RFB1 1.74 M RDRAIN1 1.6 M ROVO1 1.74 M
FIGURE 1-1:
Load Conditions for Device Timing Specifications.
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DS20091B-page 7
MCP18480
1.2 Timing Diagrams and Specifications
> 2.5V UVTH
< 2.5V OVTH = 2.5V VREFOUT
DRAINTH
GATE MA001B PWRGOOD MA000 MA001A MA002
= 5V (1)
= 12V
Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced.
FIGURE 1-2: TABLE 1-3:
Param. No. MA000
Startup Waveforms. STARTUP TIMING REQUIREMENTS
Parameter Sym TUVOVH2DTHF TDTHF2GATEPGH TDTHF2GATEFR TGATEFR2FETE Min -- -- -- -- Typ 20.2 19.3 13.1 16.1 Max Units -- -- -- -- ms ms ms ms Conditions
UVTH/OVTH High (VPOS applied) to DRAINTH falling
MA001A DRAINTH falling to PWRGOOD High MA001B DRAINTH falling to GATE Fast Ramp MA002 Note: GATE Fast Ramp to external FET fully enhanced
Minimum and maximum specifications will be provided in future revisions of this data sheet.
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MCP18480
ENABLE MA012 GATE
(1)
MA010
MA011 Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced.
FIGURE 1-3: TABLE 1-4:
Param. No. MA010 MA011 MA012 Note:
ENABLE-to-GATE Waveforms. ENABLE-TO-GATE TIMING REQUIREMENTS
Parameter Sym TENL2GATEL TENH2GATEFR TGATEFR2GATEH Min -- -- -- Typ Max Units 23.6 41 17.8 -- -- -- s ms ms Conditions
ENABLE Low to GATE Low ENABLE High to GATE Fast Ramp GATE Fast Ramp to GATE High
Minimum and maximum specifications will be provided in future revisions of this data sheet.
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DS20091B-page 9
MCP18480
VREFIN + V OVO
OVTH
VREFIN + VOVO - 20 mV
GATE(1) MA020 MA021
MA022
Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced.
FIGURE 1-4: TABLE 1-5:
Param. No. MA020 MA021 MA022 Note:
OVTH-to-gate Waveform.
OV TH-TO-GATE TIMING REQUIREMENTS Parameter Sym TOVH2GATEL TOVL2GATEFR TGATEFR2GATEH Min -- -- -- Typ Max Units 58.4 40.8 17.8 -- -- -- s s ms Conditions
OVTH High to GATE Low OVTH Low to GATE Fast Ramp GATE Fast Ramp to GATE High
Minimum and maximum specifications will be provided in future revisions of this data sheet.
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MCP18480
UVTH VREFIN - 262 mV VREFIN
GATE (1)
MA030 MA033 MA032
MA031 Note 1: This voltage is determined by the threshold voltage of the external FET. This voltage needs to ensure the external FET is fully enhanced.
FIGURE 1-5: TABLE 1-6:
Param. No. MA030 MA031 MA032 MA033
UVTH-to-gate Waveform UVTH-TO-GATE TIMING REQUIREMENTS
Parameter Sym TUVL2GATEF TGATEH2GATEL TUVH2GATEFR TGATEFR2GATEH Min -- -- -- -- Typ(1) 108 25.8 40.4 58.4 Max Units -- -- -- -- s s ms ms Conditions CUVD = 800 nF
UVTH Low to GATE Falling Edge GATE High to GATE Low ENABLE High to GATE Fast Ramp GATE Fast Ramp to GATE High
Note 1: Data in the Typical ("Typ") column is at 5V, 25C, unless otherwise stated. 2: Minimum and maximum specifications will be provided in future revisions of this data sheet.
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DS20091B-page 11
MCP18480
Foldback Current-Limiting
SENSE
GATE
MA041 Recovery from Foldback Current-Limiting
SENSE
GATE
MA042 Circuit Breaker Current-Limiting SENSE
GATE MA043
FIGURE 1-6: TABLE 1-7:
Param. No. MA041 MA042 MA043 Note:
Sense-to-gate Waveform. SENSE-TO-GATE TIMING REQUIREMENTS
Parameter Sym TGATECL2GATEO TGATECL TSENSEH2GATEO Min -- -- -- Typ Max Units 5.5 10.2 3.6 -- -- -- ms ms ms Conditions CTIMER = 0.68 F RISET = 124 k CTIMER = 0.68 F RISET = 124 k
GATE Current Limit to GATE Off GATE Current Limit Recovery SENSE High to GATE Off
Minimum and maximum specifications will be provided in future revisions of this data sheet.
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MCP18480
External Short Condition On-Board
RESTART ENABLE SENSE GATE Timer MA054 MA053 MA055
MA051 MA050
FIGURE 1-7: TABLE 1-8:
Param. No. MA050 MA051 MA053 MA054 MA055
Current Limit Waveform. CURRENT LIMIT TIMING REQUIREMENTS
Parameter Sym TSHORT2TIMERS TTIMERP TENABLEH2TIMERS TRESTARTL2TIMERS TNOSHORT2TIMERO Min -- -- -- -- -- Typ 171 5.8 30.5 30.9 5.8 Max Units -- -- -- -- -- mS sec mS mS sec CTIMER = 0.68 F RDISCH = 1.6 M CTIMER = 0.68 F RDISCH = 1.6 M CTIMER = 0.68 F RDISCH = 11.6 M CTIMER = 0.68 F RDISCH = 1.6 M Conditions
External Short to Timer period start Timer period ENABLE High to Timer period start RESTART Low to Timer period start External Short removed to Timer off Note 2
Note 1: Minimum and maximum specifications will be provided in future revisions of this data sheet. 2: This is up to one additional timer period because the external short circuit is removed asynchronously to the timer. The timer must time out before normal operation returns.
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DS20091B-page 13
MCP18480
NOTES:
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MCP18480
2.0
Note:
DC CHARACTERISTIC CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
12.400 Supply Voltage, VPOS (V)
TA = +25C TA = -5C TA = +85C
11.90 Supply Voltage, VPOS (V) 11.85 11.80 11.75 11.70 11.65 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
IPOS = 5 mA
11.900
11.400
TA = +70C
TA = -40C
10.900 Supply Current, I POS (mA)
Data taken with the minimum following conditions: VREFIN = 2.5V, ISET = 10 A
Data taken with the minimum following conditions: Minimum Supply Current to bring VPOS into regulation VREFIN = 2.5V, ISET = 10 A
FIGURE 2-1: Supply Current (IPOS) vs. Supply Voltage (VPOS).
FIGURE 2-2: Temperature.
2003 Microchip Technology Inc.
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (C)
Minimum Supply Current vs.
DS20091B-page 15
MCP18480
0.35
TA = +85C 12.0 11.0
Gate Output Vol (mV)
Gate Voltage (V)
0.30 0.25
10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 3 5 7 9 11 13 15 17 19 21 23 25 TA = -40C TA = 0C TA = +25C TA = +85C
TA = +70C
TA = 0C
TA = +25C
0.20
TA = -40C
0.15 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Supply Current (mA)
Supply Current (mA)
Data taken with the minimum following conditions: 3 mA IPOS 30 mA VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < VVREFIN VSENSE = V VNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: 3 mA IPOS 30 mA VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = V VNEG VRESTART = V VNEG (open)
FIGURE 2-3: GATE Output High-Voltage (VPOS- VGATE) vs. Supply Current (IPOS).
FIGURE 2-4: GATE Output Low-Voltage (VGATE - VNEG) vs. Supply Current (IPOS).
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MCP18480
55 Gate Pull-up Current (A) Gate Current (mA) 50 45 40 35 -40 60 55 50 45 40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Temperature (C) Temperature (C)
Data taken with the minimum following conditions: Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VGATE > 0.5V VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = V VNEG VRESTART = V VNEG (open)
FIGURE 2-5: GATE Source (Pull-Up) Current vs. Temperature.
FIGURE 2-6: GATE Sink (Pull-Down) Current vs. Temperature.
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MCP18480
-5 -15 -25 -35 -45 -55 -65 -75 -85 -95 -105 TA = +85C PWRGOOD, V OL (V) 10 15 20 25 30 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 -40 -20 0 20 40 60 80 Temperature (C)
Gate Current (uA)
TA = +25C TA = -40C -30 -25 -20 -15 -10 -5 0 5
ISET Current (uA)
Data taken with the minimum following conditions: -50 A A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V Note 1: VGATE > 0.5V VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: ILOAD = 1 mA IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-7: ISET Pin Current.
GATE Source Current vs.
FIGURE 2-8: PWRGOOD Output Low Voltage (VOL) vs. Temperature.
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MCP18480
PWRGOOD Output Impedance (Ohms) 97.5 PWRGOOD VOH (%VPOS ) 97.3 97.0 96.8 96.5 96.3 96.0 95.8 95.5 -40 -20 0 20 40 60 80 Temperature (C) 245 235 225 215 205 195 185 175 165 155 -40 -20 0 20 40 Temperature (C) 60 80
Data taken with the minimum following conditions: ILOAD = -1 mA IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-9: PWRGOOD Output HighVoltage (VOH) vs. Temperature.
FIGURE 2-10: PWRGOOD Output HighImpedance vs. Temperature.
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MCP18480
PWRGOOD Output Impedance (Ohms) 250 240 230 220 210 200 190 180 -40 -20 0 20 40 60 80 Temperature (C)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-11: PWRGOOD Output LowImpedance vs. Temperature.
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MCP18480
2.498 2.497 2.496 VREFOUT (V) 2.495 2.494 2.493 2.492 2.491 2.490 3 4 5 6 7 8 9 10 11 12 13 14 15 Supply Current, I POS (mA)
TA = -40C TA = 0C TA = +70C TA = +85C TA = +25C
3.0 2.5 VREFOUT (V) 2.0 1.5 1.0 0.5 0.0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 LOAD Current (mA) TA = +25C TA = +70C TA = +85C TA = -40C TA = 0C
Data taken with the minimum following conditions: 3 mA IPOS 30 mA VREFIN = 2.5V, ISET = 10 A
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, Iset = 10 A
FIGURE 2-12: (IPOS).
VREFOUT vs. Supply Current
FIGURE 2-13:
VREFOUT vs. LOAD.
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MCP18480
2.2 Timer Pin Current (uA) 2.0 1.8 1.6 1.4 1.2 1.0
TA = -40C TA = +25C TA = +85C
Timer Pin Current (A)
0 -25 -50 -75 -100 -125 -150 -175 -200 -225
TA = +85C TA = -40C TA = +25C
TA = +85C TA = -40C TA = +25C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RDISCH Current (uA)
Data taken with the minimum following conditions: -50 A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: -50 A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE 100mV VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-14: TIMER Pin Output Low Current vs. R DISCH Current.
FIGURE 2-15: TIMER Pin Output High Current vs. ISET Current.
DS20091B-page 22
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 ISET Current (uA)
2003 Microchip Technology Inc.
MCP18480
0 UVD Pin Current (A) -10 -20 -30 -40 -50 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 ISET Pin Current (A)
TA = +85C TA = +25C TA = -40C TA = 0C TA = +70C
112 DRAIN TH Voltage (mV) 111 110 109 108 107 106 105
TA = +25C TA = +70C
TA = +85C
TA = 0C TA = -40C
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Supply Current, IPOS (mA)
Data taken with the minimum following conditions: -50 A < IISET < 50 A (IISET 0) IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V Note 1: VUVTH < VVREFIN VOVTH < V VREFIN VSENSE = V VNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: 3 mA IPOS 30 mA VREFIN = 2.5V, ISET = 10 A Determined by PWRGOOD signal Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-16: Current.
UVD Pin Current vs. ISET Pin
FIGURE 2-18: DRAINTH Threshold Voltage vs. Supply current (IPOS).
1.35 ISET Pin Voltage (V) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 2.00
TA = +85C TA = +25C TA = 0C TA = -40C TA = +70C
2.10
2.20
2.30
2.40
2.50
2.60
VREFIN Pin Voltage (V)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) Iset = 10 A
FIGURE 2-17: Pin Voltage.
ISET Pin Voltage vs. VREFIN
2003 Microchip Technology Inc.
DS20091B-page 23
MCP18480
870 RDISCH Current (nA)
RDISCH Voltage (V) 1.310 TA = -40C 1.300 1.290 1.280 1.270 1.260 1.250 0 5
TA = +25C TA = -40C TA = +85C
860 850 840 830 820 5 10 15
TA = +25C
TA = +85C
20
25
10
15
20
25
30
35
40
45
50
Supply Current, IPOS (mA)
RDISCH Current (uA)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A RDISCH = 16 M Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A IRDISCH from 100 nA to 10 A (500 nA steps) Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-19: Current (IPOS).
R DISCH Current vs. Supply
FIGURE 2-20: Current.
RDISCH Voltage vs. RDISCH
DS20091B-page 24
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MCP18480
1.43 Enable/Restart, VIL (V) 1.42 1.41 1.40 1.39 1.38 1.37 1.36 -40 -20 0 20 40 60 80 Temperature (C)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Determined by GATE voltage Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VRESTART = V VNEG (open)
FIGURE 2-21: ENABLE/RESTART Pin Trip Point Voltage vs. Temperature.
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DS20091B-page 25
MCP18480
87.0 86.5 86.0 85.5 85.0 84.5 84.0 83.5 83.0 82.5 82.0 -40 -20 0 20 40 Temperature (C) 60 80
-152.0 -152.3 Timer Current (uA) -152.5 -152.8 -153.0 -153.3 -153.5 -153.8 -154.0 -40 -20 0 20 40 60 80 Temperature (C)
Data taken with the minimum following conditions: RDISCH = 16 M IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A 0.1V VTIMER 1.25V Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VNEG, I into device VNEG + 100mV, I out of device VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Timer Current (nA)
Data taken with the minimum following conditions: RDISCH = 16 M IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A 0.1V VTIMER 1.25V Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = VNEG, I into device VNEG + 100mV, I out of device VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-22: vs. Temperature.
TIMER Output Sink Current
FIGURE 2-23: TIMER Output Source Current vs. Temperature.
DS20091B-page 26
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MCP18480
CL Pin Offset Voltage, VOS (mV) 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 -2.50 -40 -20 0 20 40 60 80 Temperature (C)
VSENSE = 40 mV
SENSE Pin Voltage (mV)
VSENSE = 30 mV
55 50 45 40 35 30 25 20 15 10 -40 -20 0 20 40 60 80 Temperature (C)
Vfb = 0.5V Vfb = 1V Vfb = 0V
V SENSE = 20 mV
Vfb = 0.25V
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VSENSE = 25mV VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use TIMER pin as indicator Note 1: VUVTH > VVREFIN VOVTH < V VREFIN VVFB = VNEG, VNEG+ 250mV, VNEG+500mv, VNEG+1V VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-24: vs. Temperature.
CL pin Input Offset Voltage
FIGURE 2-25: vs. Temperature.
SENSE Pin Input Threshold
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DS20091B-page 27
MCP18480
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0.0 OVTH Input High Voltage (V)
TA = +85C TA = -40C TA = +70C TA = +25C TA = +0C
OVTH Input Low Voltage, VIL (V)
2.480 2.479 2.478 2.477 2.476 2.475 2.474 0 1 2 3
TA = +70C TA = +25C
TA = +85C
TA = 0C TA = -40C
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
4
5
6
7
8
OVO Voltage (V)
OVO Voltage (V)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) OVO = VNEG to 8V VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator Note 1: VUVTH > VVREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) OVO = VNEG to 8V VREFIN = 2.5V, ISET= 10 A Use PWRGOOD pin as indicator Note 1: VUVTH > VVREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-26: vs. OVO Voltage.
OV TH Input Rising Threshold
FIGURE 2-27: OVTH Input Falling Threshold vs. OVO Voltage.
DS20091B-page 28
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MCP18480
-9.90
TA = -40C
UVHYS Pin Impedance (Ohms)
45000 40000 35000 30000 25000 20000 15000 10000 5000 0 -40 -20 0 20 40 60 80 Temperature (C)
ON OFF
UVD Current (uA)
-9.95
TA = 0C
-10.00
TA = +25C
-10.05
TA = +70C
-10.10
TA = +85C
-10.15 5 10 15 20 25 30 Supply Current, IPOS (mA)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) self regulating POS at VREFIN = 2.5V, ISET = 10 A Note 1: VUVTH < VVREFIN VOVTH < V VREFIN VSENSE = V VNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) UVTH < VREFIN, UV TH > VREFIN VREFIN = 2.5V, ISET = 10 A Note 1: VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-28: Current (IPOS).
UVD Current vs. Supply
FIGURE 2-29: Temperature.
UVHYS Pin Impedance vs.
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DS20091B-page 29
MCP18480
UVTH Falling Threshold (V) -40 -20 0 20 40 60 80 UVTH Rising Threshold (V) 2.5034 2.5032 2.5030 2.5028 2.5026 2.5024 2.5022 2.5020 2.5018 Temperature (C) 2.5035 2.5030 2.5025 2.5020 2.5015 2.5010 -40 -20 0 20 40 60 80 Temperature (C)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator Note 1: VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator Note 1: VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = VVREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
FIGURE 2-30: UVTH Input Rising Threshold vs. Temperature.
FIGURE 2-31: UVTH Input Falling Threshold vs. Temperature.
DS20091B-page 30
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MCP18480
OVTH Rising Threshold (V) OVTH Falling Threshold (V) 2.5087 2.5082 2.5077 2.5072 2.5067 2.5062 2.5057 -40 -20 0 20 40 60 80 Temperature (C) 2.4805 2.48 2.4795 2.479 2.4785 2.478 2.4775 -40 -20 0 20 40 60 80 Temperature (C)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A Use PWRGOOD pin as indicator Note 1: VOVTH < V VREFIN VSENSE = VVNEG VVFB = V VNEG VDRAINTH = V VNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = V VNEG (open)
Data taken with the minimum following conditions: IPOS = 5 mA (Enables VPOS at its self-regulating voltage) VREFIN = 2.5V, ISET = 10 A VUVHYS = VNEG Use PWRGOOD pin as indicator Note 1: VOVTH < V VREFIN VSENSE = VVNEG VVFB = VVNEG VDRAINTH = VVNEG VOVO = VVNEG VCL = V VREFIN VENABLE = 5V (open) VRESTART = VVNEG (open)
FIGURE 2-32: vs. Temperature.
OV TH Input Rising Threshold
FIGURE 2-33: OVTH Input Falling Threshold vs. Temperature.
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DS20091B-page 31
MCP18480
NOTES:
DS20091B-page 32
2003 Microchip Technology Inc.
MCP18480
3.0 PIN DESCRIPTIONS
MCP18480 PIN DESCRIPTIONS
Pin Number SSOP VPOS 1 Pin Direction I Buffer Type P Positive supply input. Internal Shunt Regulator connected between V POS and VNEG limits the potential to 12V between these two pins. A series resistor must be placed on the V POS pin to limit the current into the device. OVTH 2 I A Overvoltage protection threshold. An external resistor divider network is connected to this input pin to program the overvoltage protection threshold. The selected external resistor values for the OVTH to system ground and OVTH to VNEG resistors should have currents in the 1 mA range. A typical Overvoltage threshold is -76V. Internal hysteresis in the overvoltage input comparator will allow proper operation once VNEG falls below the selected threshold. UVTH 3 I A Undervoltage lockout threshold. An external resistor divider network is connected to this input pin to program the undervoltage lockout threshold. If the voltage on UV TH is less than VNEG + 2.5V, the undervoltage comparator will trip, indicating an Undervoltage condition. An external hysteresis resistor can be used to set the high-to-low (VTHF) threshold below the low-to-high (VTHR) threshold. For telecom network equipment, it is desirable to have shutdown occur at -38.5V and the startup set at -43.0V. UVHYS 4 I A Undervoltage internal comparator hysteresis. An external resistor is connected between this input to the UVTH input pin to adjust the hysteresis of the internal Undervoltage comparator. Since it is desirable to shut down at -38.5V and restart at -43.0V in telecom switch equipment. UVD 5 I/O A Undervoltage event delay. An external capacitor is connected to this input pin to set the delay between when the UVTH pin drops below the trip point specified by the voltage on the VREFIN pin and when the system shutdown occurs (causing the PWRGOOD pin to be driven to an inactive level and the GATE pin to be pulled to the VNEG pin voltage level). The UVD pin sources a current equivalent to the IISET (in typical applications, the IISET current equals 10 A), which charges this external capacitor while an internal comparator compares this voltage on the UVD pin to |VREFIN|/2. Typically, for telecom equipment, the system is expected to shut down when the input voltage falls below -38.5V (1.0V DC) for greater than 100 ms. Legend: TTL = TTL compatible input I = Input P = Power A = Analog ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital Description
TABLE 3-1:
Pin Name
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DS20091B-page 33
MCP18480
TABLE 3-1:
Pin Name VREFOUT
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Number SSOP 6 Pin Direction O Buffer Type A Reference output. Internal reference output voltage (typically 2.5V). Usually tied back to the VREFIN pin unless an external high-precision reference voltage is desired. Description
VREFIN
7
I
A
Reference input. This pin allows a high-precision reference voltage for the following functions: * * * * Undervoltage Comparator Overvoltage Comparator DRAIN Comparator Current Limit Timer
If the precision of the VREFOUT output voltage is acceptable, tie the VREFOUT pin to the VREFIN pin. CL 8 I A Current Limit. Input used to set the maximum current limit threshold allowed by the system via a resistor divider network (with the resistor RCL1 between the VREFIN pin and the CL pin and resistor RCL between the VNEG pin and the CL pin). If the voltage across the sense resistor exceeds the voltage on the CL pin, it implies that there is excessive current over the allowed limit and forces the GATE pin to the VNEG pin voltage level without delay. ISET 9 I A Current source set. Establishes the internal ISOURCE for the following: * Undervoltage Delay * Current Limit Timer * GATE Pin Source Current An external resistor RISET from the ISET pin must be connected to either the VNEG pin or the VREFIN pin to set IBIAS, which will then establish the current sources throughout the device. The IBIAS current is the same for either connection. Connecting the RISET resistor to the VNEG pin will establish the PWRGOOD pin output polarity to be active-high. Connecting the RISET resistor to the VREFIN pin will establish the PWRGOOD pin output polarity to be active-low. Legend: TTL = TTL compatible input I = Input P = Power A = Analog ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital
DS20091B-page 34
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MCP18480
TABLE 3-1:
Pin Name TIMER
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Number SSOP 10 Pin Direction I Buffer Type A Current Limit Timer. The value of the external capacitor (C TIMER) connected to the TIMER pin sets the two time periods used during a current-limit event. These are: * The time that the GATE pin will limit the current through the external FET * The time that the GATE pin will disable the external FET During current limit, a pull-up current source charges up the external capacitor. Until the voltage on the TIMER pin reaches VREFIN/2, the GATE pin is driven to maintain a reduced current flow determined by the VDS of the external FET. While the capacitor is being discharged by the pull-down current (pullup current is off), the GATE pin is at VNEG and the PWRGOOD pin is deasserted. When the TIMER voltage falls below approximately 100 mV, the GATE pin turns on, if the RESTART pin is low, to reset the internal fault latch. If the RESTART pin is high, the GATE pin remains off until the ENABLE pin is forced low. It is then forced high or the RESTART pin is forced low (asserted). The PWRGOOD pin reasserts after the voltages on the DRAIN TH and GATE pins meet the appropriate conditions. The TIMER pin pull-up current is proportioned to the IISET current (approximately a multiple of 16). Description
VNEG
11
I
P
Negative supply input. The negative voltage applied to the board by the backplane (typically the most negative voltage in the system).
RDISCH
12
I
A
External MOSFET activation delay. An external resistor (RRDISCH) is connected between the RDISCH pin and the VNEG pin and is used to set the delay between the deactivation and activation of the external pass MOSFET during a current-limit event. The delay is set by the values of the external capacitor (CTIMER) and the external resistor (RRDISCH). The formulas are: TDEACT = (CTIMER x R ISET) / 16 TACT = (9.2 x R RDISCH x CTIMER)
Legend: TTL = TTL compatible input I = Input P = Power A = Analog
ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital
2003 Microchip Technology Inc.
DS20091B-page 35
MCP18480
TABLE 3-1:
Pin Name SENSE
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Number SSOP 13 Pin Direction I Buffer Type A Over-current sense. The voltage on the SENSE input pin is used to detect over-current conditions in the load connected to the external MOSFET. This pin is directly connected to the source of the MOSFET, with an external resistor (RSENSE) (typically a low resistance) connected between the source of the MOSFET and VNEG. Description
GATE
14
O
A
MOSFET gate driver. The GATE output pin attaches to the gate of the external MOSFET. The voltage on the GATE pin is pulled to the voltage on the VNEG pin whenever the voltage on the UVTH pin is less than the voltage on the VREFIN pin, or the voltage on the OVTH pin is greater than the voltage on the VREFIN pin. The GATE pin is also pulled to the voltage on the VNEG pin when the ENABLE input pin is low. When current limit is reached, the voltage on the GATE pin is adjusted to maintain a constant voltage across the RSENSE resistor while the CTIMER capacitor starts to charge. When the voltage on CTIMER exceeds VREFIN/2, the GATE pin is pulled to VNEG to turn off the external MOSFET. A RC network can be added from the GATE pin to the drain of the external MOSFET, along with a capacitor from the GATE pin to the VNEG pin, to control the slew rate of the GATE pin.
VFB
15
I
A
The GATE pin pull-up current is proportioned to the IISET current. External MOSFET drain monitor. The VFB input pin monitors the voltage at the drain of the external power MOSFET switch with respect to the voltage on the VNEG pin for use by the internal foldback circuitry. An external resistor divider network (R FB1 and RFB2) is attached between the drain of this external MOSFET and the VNEG pin (RFB1 is connected between the drain of the external MOSFET and the VFB pin, while RFB2 is connected between the V FB pin and the VNEG pin). This prevents high-voltage breakdown of the VFB input.
DRAINTH
16
I
A
MOSFET drain comparator threshold. This pin is used during the power-up sequence of the inserted board, and after any fault condition that `turns off' the GATE pin drive. The voltage on the pin indicates when the external FET is fully enhanced by comparing the pin voltage to an internal reference voltage (approximately 100 mV derived from the internal band gap reference). An external resistor divider network (RDRAIN1 and RDRAIN2) is attached between the drain of this external MOSFET and the VNEG pin (RDRAIN1 is connected between the drain of the external MOSFET and the DRAINTH pin while RDRAIN2 is connected between the DRAINTH pin and the VNEG pin).
Legend: TTL = TTL compatible input I = Input P = Power A = Analog
ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital
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MCP18480
TABLE 3-1:
Pin Name OVO
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Number SSOP 17 Pin Direction I Buffer Type A Overvoltage detect. Typically for normal operation. This pin is tied to V NEG. This feature allows the overvoltage detection input to monitor an overvoltage condition across the power module. The voltage is sensed at the drain of the external MOSFET. The voltage across the load is internally determined based upon: * The voltage difference between system ground and the voltage on the VNEG pin * The voltage difference between the drain of the external FET and the voltage on the VNEG pin An external resistor divider network (R OVO1 and ROVO2) is attached between the drain of the external MOSFET and the VNEG pin (ROVO1 is connected between the drain of the external MOSFET and the OVO pin, while ROVO2 is connected between the OVO pin and the VNEG pin). When the voltage across the external MOSFET (source-to-drain) equals system ground voltage (- VNEG +), the maximum desired load voltage, the GATE pin is forced to the voltage on the VNEG pin (disabling the external MOSFET). To detect Overvoltage on the board (instead of the load) directly, connect the OVO pin to the VNEG pin. Description
PWRGOOD
18
O
D
Power Good indicator. This state of the output is determined by four conditions. These are: * * * * Undervoltage Overvoltage Current Limit External FET is fully-enhanced (from DRAINTH pin on power-up) PWRGOOD is a CMOS logic voltage (VNEG or VNEG+12V).
PWRGOOD is active when the device has completed power-up and the system is neither in an Undervoltage or Overvoltage condition. Connecting the RISET pin to the VNEG pin configures the PWRGOOD pin to be active high. Connecting the RISET pin to the VREF pin configures the PWRGOOD pin to be active low. ENABLE 19 I TTL Enable Gate driver. Used to enable the GATE pin and assert the PWRGOOD pin. The ENABLE pin is active-high and is internally pulled up to 5V. This pin is pulled low by the user to clear the current limit latch when a currentlimit fault occurs with RESTART high, or to disable the GATE pin. H = Enable the GATE and PWRGOOD pins. L = Disables the GATE pin, deasserts the PWRGOOD pin and clears current limit latch. When the ENABLE pin is high, fault conditions will disable the GATE pin and deasserts the PWRGOOD pin. Legend: TTL = TTL compatible input I = Input P = Power A = Analog ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital
2003 Microchip Technology Inc.
DS20091B-page 37
MCP18480
TABLE 3-1:
Pin Name RESTART
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Number SSOP 20 Pin Direction I Buffer Type TTL Auto-restart enable. Enables the auto-restart feature of the device after an over-current fault. L = The internal fault latch is reset and the device attempts to restart with a frequency determined by the values of the external components CTIMER and RDISCH. H = The auto-restart is disabled, allowing the GATE pin to remain at the VNEG pin voltage after an over-current fault. Internally pulled down to the VNEG pin voltage. Description
Legend: TTL = TTL compatible input I = Input P = Power A = Analog
ST = Schmitt Trigger input with CMOS levels O = Output CMOS = CMOS-compatible input D = Digital
DS20091B-page 38
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MCP18480
4.0 APPLICATIONS INFORMATION
The MCP18480 can be programmed to have the PWRGOOD signal be either active-high or active-low via the ISET pin and the connection of the external RISET resistor (see Section 6.8.8, "Bias Block"). If the RISET resistor is connected between ISET and VNEG, the PWRGOOD output pin is an active-high signal. If the RISET resistor is connected between ISET and VREFIN, the PWRGOOD output pin is an active-low signal. For systems using an active-low-enabled DC/DC converter module, the MCP18480 should be programmed for a high-active PWRGOOD output. Tying the RISET resistor to the VNEG pin configures the PWRGOOD to be an active-high signal. The active-high PWRGOOD switches on the external NPN and the collector of the external NPN (labeled as GOODPWR) is pulled to VNEG, enabling a low-active GOODPWR and resulting in enabling the DC/DC module. For active-high DC/DC converter modules, the MCP18480 should be programmed for a low active PWRGOOD output. Connecting RISET to the VREFIN pin will enable an active-low PWRGOOD output. Refer to Figure 4-1 and Figure 4-2 for schematics. Figure 4-1 shows a typical telecom application circuit where the DC/DC module is active-high. Figure 4-2 shows a typical telecom application circuit where the DC/DC module is active-low. The polarity of the MCP18480's PWRGOOD pin (active-high or activelow) is dependant on the state of the ISET pin.
GND RBYPL 51 k SRS 5V 1 2 RUV2 RUVHYS 3 4 5 6 7 8 9 RISET 124 k Fuse 10A Ctimer 680 nF VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET RESTART 20 ENABLE 19 PWRGOOD 18 OVO 17 DRAINTH 16 VFB 15 GATE 14 SENSE 13 RDISCH 12 VNEG 11 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 SEN RPG1 110 k RPG3 680 RPG4 36 k QPG1 MPSA43 QPG2 2N5400 GOODPWR RPG5 36 k RPG6 1500 QPG3 NTE261 CBYPL 100 F 100 V VIN+ VOUT+
RZ RPOS 4 k CBYP1 + 2 F 78V Transorb ROV1 1.74 M CBYP2 10 nF ROV2 59 k 280 k 30.9 k CUVD 800 nF RUV1 453 k 24.9 k
DC/DC Converter Module ON/OFF VIN- VOUT-
10 TIMER
MCP18480
RGD 18 k CG1 RG1 100 nF 10 M1 NTE2388 RFB2 124 k RDRAIN2 115 k RFB1 1.74 M RDRAIN1 1.6 M CGD 3.3 nF
VNEG
FIGURE 4-1: Typical Operating Circuit for Telecom Applications with Active-High power Module foldback current limit enabled.
2003 Microchip Technology Inc.
DS20091B-page 39
MCP18480
GND RBYPL 51 k SRS 5V 1 2 RUV2 30.9 k CUVD 800 nF RUVHYS 280 k 3 4 5 6 7 8 9 RISET 124 k Ctimer 680 nF VPOS OV TH UVTH UVHYS UVD VREFOUT VREFIN CL ISET RESTART 20 ENABLE 19 PWRGOOD 18 OVO 17 DRAINTH 16 VFB 15 GATE 14 SENSE 13 RDISCH 12 VNEG 11 RDISCH 1.6 M RPG2 7.5 k RSENSE 0.01 CG1 R G1 100 nF 10 M1 NTE2388 RFB2 124 k RDRAIN2 115 k RFB1 1.74 M RDRAIN1 1.6 M SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 QPG2 2N5400 GOODPWR RPG5 36 k RPG6 1500 QPG3 NTE261 CBYPL 100 F 100 V VIN+ VOUT+
RZ RPOS 4 k CBYP1 + 2 F 78V Transorb ROV1 1.74 M CBYP2 10 nF ROV2 59 k RUV1 453 k 24.9 k
DC/DC Converter Module ON/OFF VIN- VOUT-
10 TIMER
MCP18480
RGD 18 k CGD 3.3 nF
VNEG
Fuse 10A
FIGURE 4-2: Typical operating circuit for telecom applications with Active-Low power Module foldback current limit enabled.
DS20091B-page 40
2003 Microchip Technology Inc.
MCP18480
The MCP18480 can typically be implemented in a backplane system in one of two methods. Figure 4-3 shows a system where the backplane integrates the MCP18480 for every slot. Figure 4-4 shows a system where the backplane does not integrate the MCP18480s and each card that will be inserted into any slot is required to integrate the MCP18480.
Card #n Card #2
MCP18480 MCP18480 MCP18480
Card #1
FIGURE 4-3:
Backplane System Block Diagram #1.
Card # n
MCP18480
Card # 2 Card # 1
MCP18480 MCP18480
FIGURE 4-4:
Backplane System Block Diagram #2.
2003 Microchip Technology Inc.
DS20091B-page 41
MCP18480
NOTES:
DS20091B-page 42
2003 Microchip Technology Inc.
MCP18480
5.0
5.1
POWER-UP
VPOS
6.0
and VNEG Connection
INTERNAL SIGNAL DESCRIPTIONS
For proper system operation, it is required that the system ground and the VNEG pin have a solid connection before voltages are applied to any logic on the board.
The figure on page 2 illustrates a block diagram of the MCP18480. Between the functional blocks, there are some signals that have been named. These signals are briefly explained in Section 6.1 thru Section 6.7.
5.2
The Board Circuitry
6.1
Undervoltage Active
After the MCP18480 has "good" voltages on the VPOS and VNEG pins, the board may have voltages applied to any of the other signals (a "good" voltage on VPOS indicates a "good" voltage on the system ground). The MCP18480 will start to source a small current to the external MOSFET to begin powering the board. This will turn on the MOSFET starting to power the external circuitry (load) of the board. The current from the GATE pin (into the external MOSFET) increases as the VDS of the MOSFET decreases. When the VDS of the MOSFET is below the voltage determined by the two resistors on the DRAINTH pin (RDRAIN1 and RDRAIN2), and the voltage on the GATE pin is greater than 8V, the PWRGOOD pin is active.
A signal that indicates (when low) that System Ground - VNEG is less then the minimum voltage.
6.2
Overvoltage Active
A signal that indicates (when low) that System Ground -VNEG is greater then the maximum voltage.
6.3
LATCHOFF
A signal that controls the GATE pin due to a timeout of the current-limiting timer.
6.4
Current Limit TIMER
A signal that controls the reduction of source current on the GATE pin and starts the voltage ramp of the current limit timer.
6.5
Current Limit Feedback
A voltage that is proportional to the VDS of the external MOSFET to set a trip point for current-limiting.
6.6
TIMEOUT
A signal that indicates the completion of the foldback time and is used to start the latchoff time.
6.7
Circuit Breaker
A signal that immediately causes the GATE pin output to be driven to VNEG upon the detection of excessive current in the external FET.
2003 Microchip Technology Inc.
DS20091B-page 43
MCP18480
6.8 DESCRIPTION OF INTERNAL BLOCKS
If the supply voltage dips below the programmed threshold, the input comparator trips the other way. The timing capacitor is released to ramp-up at the previously described rate and the Undervoltage block switches when the capacitor voltage reaches 1.25V. When the input comparator goes to a low level, the hysteresis FET is turned on and the trip point for reassertion of good VNEG reverts to -43V. While the Undervoltage Active signal is low (includes Undervoltage input filter), the GATE pin driver for the external MOSFET is disabled, the GATE pin is pulled to the voltage of the VNEG pin with a 60 mA current sink and the PWRGOOD output pin is deasserted to indicate that the input voltage is out of range.
The internal blocks shown in the MCP18480 Block Diagram on page 2 are discussed in Section 6.8.1 through Section 6.8.8. Note: Voltage levels discussed are with respect to external component values selected in Figure 4-1.
6.8.1
UV (UNDERVOLTAGE) BLOCK
The Undervoltage lockout circuit monitors the input voltage by comparing a centertap voltage on an external resistor divider to a 2.5V reference. The centertap voltage is fed into the UVTH input pin. If the voltage on the UV TH pin is below the internal 2.5V reference, the absolute magnitude of the supply voltage is too low for proper system operation, resulting in the external MOSFET being turned off. If the voltage on the UVTH pin is greater than VNEG + 2.5V, the supply voltage is above the minimal operating voltage as set by the external resistor divider network. In telecom network applications, it is common to shut down the DC/DC converter supply when the input voltage falls below -38.5V (tolerance of 1.0V) for greater than 100 ms. The system will not restart until the voltage exceeds -43.0V (tolerance of 0.5V). This voltage difference is produced by an open-drain NMOS output (the UVHYS pin) that connects an external resistor in parallel with the lower of the two resistors in the external UV divider network until the supply ramps down to -43V. When the UVTH pin exceeds VNEG + 2.5V, the internal NMOS transistor is turned off, disconnecting the external resistor connected to the UV HYS pin. The voltage at the UVTH pin increases to 2.79V. The supply voltage would have to decrease to -38.5V in order to assert the internal "Undervoltage Active" signal. An internal 10 A current source and an external capacitor connected to the UV D pin adjusts the delay between the input fault and the notification of this fault to the system. This is usually 100 ms for -48V telecomtype equipment. For customized adjustments, the time delay can be expressed as Equation 6-1.
EQUATION 6-2:
UNDERVOLTAGE HYSTERESIS
R U V1 R UVHYS = ---------------------------------------------------V U VD R UV1 ----------------- - ------------ - 1 - V R UV2 REFIN
EQUATION 6-3:
UNDERVOLTAGE CONDITION
V NEG * R UV2 V REFIN > -----------------------------------( R U V1 + R U V2 )
EQUATION 6-1:
INPUT FAULT DELAY
V REFIN * C ----------------U VD 2 = ------------------------------------------10A
T D ELAY
CUV is the capacitor connected between the UVD pin and the VNEG pin. A value of 1 F would provide a delay of about 100 ms.
DS20091B-page 44
2003 Microchip Technology Inc.
MCP18480
6.8.2 OV (OVERVOLTAGE) BLOCK 6.8.3 FET-GOOD BLOCK
The overvoltage block behaves similarly to the undervoltage block in that it monitors an input voltage by comparing a centertap voltage on an external voltage divider (on the OVTH pin) to the V REFIN pin voltage. If the centertap voltage is below the reference, the input voltage is not excessive. If the centertap voltage is greater than the VNEG + VREFIN pin voltages, the supply voltage is higher than the programmed acceptable maximum voltage limit. An internal flag is then activated to inform the MCP18480 that the input voltage has exceeded the preset limit. The "Overvoltage Active" signal deasserts when the input voltage drops back below the threshold determined by the external resistors (ROV1 and ROV2). The FET-good block monitors the voltage between the drain of the external MOSFET and on the VNEG pin at power-up. It delays assertion of PWRGOOD until the drain-to-source voltage of the external FET is acceptably low and the voltage at the GATE pin is about 8V. The comparator operation is similar to Undervoltage and Overvoltage blocks. To prevent applying excessive voltages to the gates of the FETs in the Undervoltage circuit, a resistive voltage divider is employed between ground and the VNEG pin. Similarly, the drain of the external MOSFET can be exposed to voltages at around VNEG during normal operation and as high as ground (typically 48V above VNEG). The FET good block also monitors the GATE pin. When the GATE pin becomes >VNEG +8V and the DRAINTH pin is within its programmed range, the output of the FET good block is active. The internal FET good signal goes high and remains active until a fault condition (Undervoltage, Overvoltage or Current Limit) is detected. Any of these conditions hold the PWRGOOD signal deasserted until the fault condition is removed and the external FET gate and drain voltages are acceptable.
EQUATION 6-4:
OVERVOLTAGE VOLTAGE CONDITION
V NEG * R OV2 V REFIN < -----------------------------------( R OV1 + R OV2 )
2003 Microchip Technology Inc.
DS20091B-page 45
MCP18480
6.8.4 CURRENT LIMIT BLOCK 6.8.5 TIMER BLOCK
An excessive current flowing through the external FET is sensed as a voltage across an external resistor connected between the FET's source and VNEG. The drain voltage is sensed with a resistor divider network, as shown in Figure 4-1 and Figure 4-2. The voltage tap is applied to a circuit whose output is 50 mV above VNEG when the drain of the external FET is at VNEG. The output is 12 mV when the V FB pin is VNEG +0.5V. This output voltage is the Current Limit Feedback (CLFB) signal to the gate driver block for use in the fold-back current-limiting. The CLFB voltage serves as the reference for a comparator whose other input monitors the voltage across the current limit sense resistor in series with the source of the external FET. When the SENSE pin exceeds the voltage on CLFB, a comparator output goes high to start the timer (see Section 6.8.5). The VDS dependent threshold for the current limit helps keep the FET within its safe operating area. Another comparator in the current-limiting block watches the SENSE pin for potentially catastrophic over-current conditions, which require immediate termination of conduction in the pass MOSFET. The output of this comparator trips a comparator used in the TIMER block to skip the first part of the timeout cycle and go straight to the "off" period. In some cases, the user may want to program the system to shut off immediately if there is a short-circuit condition that exceeds a desired level. To use this feature, connect a divider between the VREFIN pin and the VNEG pin, with its centertap at the CL input pin. The circuit breaker current that would trigger this mode is given by Equation 6-5. Since the external FET can survive brief over-current episodes, it is unnecessary to turn off the FET instantly when the current rises too high (see external FET data sheet). The timer circuit uses the output of the comparator in the current-limiting block to begin charging an external capacitor with 16 * IRISET (typically 160 A) when an over-current condition is detected. When the voltage on the capacitor ramps up to 1.25V, a comparator output goes high. This output goes to another block that tells the gate driver to turn the external FET off and deassert the PWRGOOD pin. The complementary output of the timer changes the state of a hysteresis circuit that drops the reference input of the comparator to VNEG + 100 mV ( 10 mV). When the FET is off, the current through it drops to zero, so that the voltage across the current sense resistor also goes to zero and the current limit signal to the timer block goes away. The timer capacitor starts to discharge at a rate set by the external resistor, RDISCH. Equation 6-7 shows the equations used to calculate the current at the TIMER pin. This current is used for other calculations.
EQUATION 6-7:
TIMER PIN CURRENT CALCULATIONS
Typical Minimum Maximum
I TIMER = 16 * IRISET I TIMER = 10 * IRISET I TIMER = 20 * IRISET
EQUATION 6-5:
CIRCUIT BREAKER THRESHOLD
Legend: IRISET is the current through the external RISET resistor The delay between the inception of the over-current condition and the deactivation of the FET is given by Equation 6-8.
I CAT
V REFIN ------------------------------- * R CL2 R CL1 + R CL2 = ------------------------------------------------------R SENSE
If this function is not needed in a particular application, it can be disabled by connecting the CL pin to the VREFIN pin. Equation 6-6 shows the current of the CL pin during current-limiting.
EQUATION 6-8:
OVER-CURRENT FAULT DELAY
C TIMER T CLD 1 = ------------------ * 1.25 ITIMER The time required to reset the timer and reactivate the gate driver is given by Equation 6-9.
EQUATION 6-6:
I CL V SENSE = -----------------R SENSE
CL PIN CURRENT
> 0.5V
VFB
EQUATION 6-9:
0V 12 mV
OVER-CURRENT REACTIVATION DELAY
V SENSE
V DS x R FB2 = 0.76 x 0.05V - ------------------------------ + 0.012V R FB1 + R FB2
VSENSE
50 mV
T CLD2 = 9.2 * C TIMER * R DISCH As described above, the timer circuit operates as a free-running, multi-vibrator, if RESTART is low.
for VFB > 0.5V, VSENSE = 0.012V
DS20091B-page 46
2003 Microchip Technology Inc.
MCP18480
6.8.6 LATCH BLOCK 6.8.8 BIAS BLOCK
A current limit latch circuit determines whether, following the timeout period resulting from an over-current condition, the external FET should be latched-off until reactivated by an external signal, or be allowed to restart automatically following the timer cycle. If the RESTART input is low, the part will restart and the gate drive to the external MOSFET will be restored automatically. If the RESTART pin is high, a current limit event will turn the FET off after the programmed delay and maintain an off condition until the ENABLE pin or RESTART pin is pulled low momentarily. The internal voltage generation or bias block generates the biasing currents for all internal blocks. It also provides a 2.5V reference voltage that is brought out to the VREFOUT pin. This output pin is usually fed back into the VREFIN pin. However, an externally-generated 2.5V reference voltage may be directly connected to the VREFIN pin, while leaving the VREFOUT pin unconnected. A VREFIN/2 voltage is generated within the bias block, which is used as reference in the other blocks. A internal shunt regulator limits the internal circuitry to 12V. An external current-limiting resistor in series with VPOS absorbs the excess voltage. The resulting regulated 12V source is used in the gate drive block and PWRGOOD output circuit. The 12V source is also stepped-down to generate a 5V regulated source. Most of the other circuitry and blocks operate with the internally-generated 5V.
6.8.7
GATE DRIVE BLOCK
The GATE drive block sources a current equal to the voltage at CLFB divided by 1 k to the gate of the external MOSFET. So the current sourced from the GATE pin is determined by the VDS of the external FET. This current, and the external capacitors around the FET, control the slew rate of the drain of the external FET, limiting the current that would otherwise have to be diverted from other boards on the backplane. In the event of a problem (Overvoltage, Undervoltage or current limit), the gate of the external FET is pulled down with 60 mA. During normal operation, the GATE pin ramps up to about 12V, sending the external FET deeply into the triode region. If the drain current becomes excessive while the drain-to-source voltage is high, the inverting input of the op amp is driven to the CLFB voltage by the current-limiting block, causing a reduction in the drive to the external FET to reduce the current through it. This foldback current-limit remains active until the voltage on CTIMER reaches VREFIN/2, after which the GATE output pin is pulled to VNEG for the duration of the timeout period, or until ENABLE is cycled low momentarily. For applications in which it is undesirable to have the drain current track the VDS of the external pass FET in current limit, the user can tie the VFB pin to the VREF or VNEG pin. This will make the MCP18480 try to force the drain current to 12 mV/R SENSE or 50 mV/R SENSE, respectively, until the TIMER block times out. If foldback current-limiting is not desired at all, set the divider associated with the CL pin to detect the desired current in order to shut off the GATE immediately. A voltage on the GATE pin higher than about 8V is one condition for the PWRGOOD pin to be asserted. Any fault condition that causes the GATE pin voltage to be pulled to VNEG deasserts the PWRGOOD pin. On startup, a NMOS transistor with a resistor pulling its gate up holds the GATE pin down until the MCP18480 is properly biased.
EQUATION 6-10:
EXTERNAL RISET CURRENT
V REFIN ----------------2 = ----------------------R ISET
I RISET Note:
The direction of the current is dependant on where the external RISET resistor is connected (the ISET pin to either the VNEG pin or the VREFIN pin).
6.8.9
POWER GOOD BLOCK
The "power good" block monitors the state of the OV active, the UV active, the current limit circuitry, and output of the FET good block to generate the PWRGOOD output signal.
2003 Microchip Technology Inc.
DS20091B-page 47
MCP18480
NOTES:
DS20091B-page 48
2003 Microchip Technology Inc.
MCP18480
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
20-Lead SSOP Example:
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
MCP18480 I/SS 0348058
Legend:
XX...X YY WW NNN
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, and traceability code.
2003 Microchip Technology Inc.
DS20091B-page 49
MCP18480
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c
A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0
INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10
MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5
MAX
1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072
DS20091B-page 50
2003 Microchip Technology Inc.
MCP18480
APPENDIX A:
Revision A
This is a new data sheet
REVISION HISTORY
Revision B
* Add device characterization information * Enhanced functional description
2003 Microchip Technology Inc.
DS20091B-page 51
MCP18480
NOTES:
DS20091B-page 52
2003 Microchip Technology Inc.
MCP18480
APPENDIX B: MCP18480 SCHEMATICS
This appendix contains the schematics for the MCP18480 Evaluation Board.
2003 Microchip Technology Inc.
DS20091B-page 53
GND VIN+ VOUT+ RBYPL 51 k SRS SEN R PG1 110 k RPG6 1500 RPG5 36 k QPG2 2N5400 QPG3 NTE261
DS20091B-page 54
RZ 24.9 k RUV1 453 k
CBYPL 100 F 100 V
MCP18480
ROV1 RPOS 4 k 1.74 M
MCP18480
1 2 3 OVTH UVTH UVHYS UVD VREFOUT VREFIN CL RDISCH 1.6 M 4 5 6 7 8 9 ISET 10 TIMER CTIMER 680 nF GATE 14 SENSE 13 RDISCH 12 VNEG 11 OVO 17 DRAIN TH 16 VFB 15 VPOS RESTART 20 ENABLE 19 PWRGOOD 18 R 5V PG3 680 RPG4 36 k Q PG1 MPSA43
DC/DC Converter Module ON/OFF VIN- VOUT-
CBYP1 + 2 F RUVHYS RUV2 280 k 30.9 k CUVD 800 nF
CBYP2 10 nF
78V Transorb
ROV2 59 k
RISET 124 k
RGD 18 k CG1 RG1 100 nF 10 M1 NTE2388 RFB2 124 k RDRAIN2 115 k ROVO2 59 k RFB1 1.74 M RDRAIN1 1.6 M ROVO1 1.74 M CGD 3.3 nF
VNEG
Fuse 10A
RPG2 7.5 k RSENSE 0.01
2003 Microchip Technology Inc.
FIGURE B-1:
Typical Operating Circuit for Telcom Applications with Active-High Power Module - Foldback Current Limit Enabled.
GND VIN+ VOUT+ RBYPL 51 k SRS SEN R PG1 110 k RPG5 36 k RPG6 1500 QPG2 2N5400 QPG3 NTE261
RZ 24.9 k RUV1 453 k
CBYPL 100 F 100 V
ROV1 RPOS 4 k 1.74 M
MCP18480
1 2 3 OVTH UVTH UVHYS UVD VREFOUT VREFIN CL RDISCH 1.6 M 4 5 6 7 8 9 ISET 10 TIMER CTIMER 680 nF GATE 14 SENSE 13 RDISCH 12 VNEG 11 OVO 17 DRAIN TH 16 VFB 15 VPOS RESTART 20 ENABLE 19 PWRGOOD 18 R 5V PG3 680 RPG4 36 k Q PG1 MPSA43
2003 Microchip Technology Inc.
DC/DC Converter Module ON/OFF VIN- VOUT-
CBYP1 + 2 F RUVHYS RUV2 280 k 30.9 k CUVD 800 nF
CBYP2 10 nF
78V Transorb
ROV2 59 k
RISET 124 k
RGD 18 k CG1 RG1 100 nF 10 M1 NTE2388 RFB2 124 k RDRAIN2 115 k ROVO2 59 k RFB1 1.74 M RDRAIN1 1.6 M ROVO1 1.74 M CGD 3.3 nF
VNEGA 1
Fuse 10A
RPG2 7.5 k RSENSE 0.01
MCP18480
DS20091B-page 55
FIGURE B-2:
Typical Operating Circuit for Telcom Applications with Active-Low Power Module - Foldback Current Limit Enabled.
DS20091B-page 56
RZ 24.9 k
RBYPL 51 k SRS 5V SEN RPG1 110 k RPG5 36 k RPG6 1500 Q PG2 2N5400 RPG3 680 RPG4 36 k Q PG1 MPSA43
CBYPL RLOAD 100 F 75
MCP18480
RPOS 4 k
ROV1 1.74 M
RUV1 453 k
MCP18480
CBYP1 + 2 F RUVHYS 280 k
CBYP2 10 nF
ROV2 59 k CUVD 800 nF
RUV2 30.9 k
1 2 3 4 5 6 7 8 9 VNEG 11 RDISCH 1.6 M RGD 18 k RPG2 7.5 k RSENSE 0.01 C G1 RG1 100 nF 10 M1 NTE2388 R FB2 124 k RDRAIN2 115 k ROVO2 59 k
VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET RESTART ENABLE PWRGOOD OVO DRAIN TH VFB GATE SENS RDISCH 20 19 18 17 16 15 14 13 12
QPG3 NTE261
10 TIMER RISET 124 k C TIMER 680 nF
CGD 3.3 nF
VNEG
RFB1 1.74 M RDRAIN1 1.6 M ROVO1 1.74 M
2003 Microchip Technology Inc.
FIGURE B-3:
Evaluation Board Schematic (Active-Low Power Module - Foldback Current Limit Enabled).
RZ 24.9 k
RBYPL 51 k SRS 5V SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 QPG2 2N5400 RPG5 36 k RPG6 1500
CBYPL RLOAD 100 F 75
2003 Microchip Technology Inc.
RPOS 4 k
ROV1 1.74 M
RUV1 453 k
MCP18480
CBYP1 + 2 F RUVHYS 280 k
CBYP2 10 nF
ROV2 59 k CUVD 800 nF RISET 124 k RDISCH 1.6 M
RUV2 30.9 k
1 2 3 4 5 6 7 8 9 10 CTIMER 680 nF
VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENS RDISCH VNEG 20 19 18 17 16 15 14 13 12 11
Q PG3 NTE261
RGD 18 k RPG2 7.5 k RSENSE 0.01 CG1 RG1 100 nF 10 M1 NTE2388 RFB2 124 k RDRAIN2 115 k ROVO2 59 k RFB1 1.74 M RDRAIN1 1.6 M ROVO1 1.74 M CGD 3.3 nF
VNEG
MCP18480
DS20091B-page 57
FIGURE B-4:
Evaluation Board Schematic (Active-High Power Module - Foldback Current Limit Enabled).
DS20091B-page 58
RZ 24.9 k
RBYPL 51 k SRS 5V SEN RPG1 110 k RPG5 36 k RPG6 1500 Q PG2 2N5400 RPG3 680 RPG4 36 k Q PG1 MPSA43
CBYPL RLOAD 100 F 75
MCP18480
RPOS 4 k
ROV1 1.74 M
RUV1 453 k
MCP18480
CBYP1 + 2 F RUVHYS 280 k
CBYP2 10 nF
ROV2 59 k CUVD 800 nF RCL1 (Note) 210 k RCL2 (Note) 40.2 k 10 TIMER RISET 124 k C TIMER 680 nF VNEG 11 RDISCH 1.6 M
RUV2 30.9 k
1 2 3 4 5 6 7 8 9
VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET RESTART ENABLE PWRGOOD OVO DRAIN TH VFB GATE SENS RDISCH 20 19 18 17 16 15 14 13 12
QPG3 NTE261
RGD 18 k RPG2 7.5 k RSENSE 0.01 C G1 RG1 100 nF 10 M1 NTE2388 CGD 3.3 nF
VNEG
RDRAIN2 115 k ROVO2 59 k
RDRAIN1 1.6 M ROVO1 1.74 M
2003 Microchip Technology Inc.
FIGURE B-5:
Evaluation Board Schematic (Active-Low Power Module - Circuit Breaker Current Limit Enabled).
RZ 24.9 k
RBYPL 51 k SRS 5V SEN RPG1 110 k RPG3 680 RPG4 36 k Q PG1 MPSA43 QPG2 2N5400 RPG5 36 k RPG6 1500
CBYPL RLOAD 100 F 75
2003 Microchip Technology Inc.
RPOS 4 k
ROV1 1.74 M
RUV1 453 k
MCP18480
CBYP1 + 2 F RUVHYS 280 k
CBYP2 10 nF
ROV2 59 k CUVD 800 nF RCL1 (Note) 210 k RCL2 (Note) RISET 40.2 k 124 k CTIMER 680 nF RDISCH 1.6 M
RUV2 30.9 k
1 2 3 4 5 6 7 8 9 10
VPOS OVTH UVTH UVHYS UVD VREFOUT VREFIN CL ISET TIMER RESTART ENABLE PWRGOOD OVO DRAINTH VFB GATE SENS RDISCH VNEG 20 19 18 17 16 15 14 13 12 11
Q PG3 NTE261
RGD 18 k RPG2 7.5 k RSENSE 0.01 CG1 RG1 100 nF 10 M1 NTE2388 CGD 3.3 nF
VNEG
RDRAIN2 115 k ROVO2 59 k
RDRAIN1 1.6 M ROVO1 1.74 M
MCP18480
DS20091B-page 59
FIGURE B-6:
Evaluation Board Schematic (Active-High Power Module - Circuit Breaker Current Limit Enabled).
MCP18480
NOTES:
DS20091B-page 60
2003 Microchip Technology Inc.
MCP18480
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples:
a) b)
Device MCP18480: MCP18480T: -48V Hot Swap Controller -48V Hot Swap Controller (Tape and Reel)
MCP18480-I/SS = Industrial Temp., SSOP package MCP18480T-I/SS = Tape and Reel, Industrial Temp., SSOP package
Temperature Range Package
I
= -40C to +85C
SS = Plastic SSOP (209 mil, Body), 20-lead
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.
DS20091B-page 61
MCP18480
NOTES:
DS20091B-page 62
2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2003 Microchip Technology Inc.
DS20091B - page 63
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Marketing Support Division Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Austria
Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
China - Hong Kong SAR
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Phoenix
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-82966626
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Germany
Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Italy
Microchip Technology SRL Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
India
Microchip Technology Inc. India Liaison Office Marketing Support Division Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
03/25/03
DS20091B-page 64
2003 Microchip Technology Inc.

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